With rapid development of Internet technologies, users raise higher requirements on network data processing performance of a Central Processing Unit (CPU).
A series of CPUs based on an Intel® X86 platform (X86 CPU) are general purpose central processing units. Because the X86 CPU lacks a corresponding hardware acceleration engine when performing some data operations or processing related to a network function, processing performance of an entire system is not high. In order to solve this problem, generally some coprocessor chips are added to a periphery of the X86 CPU, and work related to network data processing is transplanted into the coprocessor chips for implementation. Packet data transmission between these coprocessor chips and the X86 CPU is generally implemented using a peripheral component interconnect express (PCIe) link.
For example, after receiving packet data from a network side, a coprocessor chip sends the packet data to an X86 CPU through a PCIe link for processing. After completing processing on the packet data, the X86 CPU sends processed packet data back to the coprocessor chip through a PCIe link. Finally the coprocessor chip sends the processed packet data to the network side for output. In actual application, data transmission may also be performed multiple times between the coprocessor chip and the X86 CPU through a PCIe link.
During the foregoing data processing, transmission of packet data between the X86 CPU and the coprocessor chip through the PCIe link imposes a high requirement on bandwidth of the PCIe link; however, because a PCIe bus is a bus protocol of a control type, packet data transmission efficiency is not high.